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Crimzon(R) ZLR32300
Z8(R)Low-Voltage ROM MCU with Infrared Timers
Product Specification
Maxim Integrated Products Inc. 120 San Gabriel Drive, Sunnyvale CA 94086
Maxim Integrated Products 120 San Gabriel Drive Sunnyvale, CA 94086 United States 408-737-7600 www.maxim-ic.com
Copyright (c) 2009 Maxim Integrated Products Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. Maxim retains the right to make changes to its products or specifications to improve performance, reliability or manufacturability. All information in this document, including descriptions of features, functions, performance, technical specifications and availability, is subject to change without notice at any time. While the information furnished herein is held to be accurate and reliable, no responsibility will be assumed by Maxim for its use. Furthermore, the information contained herein does not convey to the purchaser of microelectronic devices any license under the patent right of any manufacturer. Maxim is a registered trademark of Maxim Integrated Products, Inc. All other products or service names used in this publication are for identification purposes only, and may be trademarks or registered trademarks of their respective companies. All other trademarks or registered trademarks mentioned herein are the property of their respective holders. Z8 is a registered trademark of Zilog, Inc. Crimzon is a registered trademark of Universal Electronics Inc.
PS022613-0409
Crimzon(R) ZLR16300 Product Specification
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Revision History
Each instance in the Revision History table reflects a change to this document from its previous revision. For more details, refer to the corresponding pages and appropriate links in the table below.
Date April 2009 February 2008 January 2008 August 2007 February 2007 May 2006 December 2005
Revision Level 13 12 11 10 09 08 07
Description Changed to Maxim product Updated the Ordering Information section. Updated the Ordering Information section. Updated the Disclaimer section and implemented style guide. Updated Low-Voltage Detection Register-- LVD(D)0CH. Added Pin 22 to SMR Block input, Figure 32. Updated section clock and Input/output port.
Page Number All 92 92 All 60 54 50, 14
PS022613-0409
Revision History
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Table of Contents
Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Development Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 XTAL1 Crystal 1 (Time-Based Input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 XTAL2 Crystal 2 (Time-Based Output) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Input/Output Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 RESET (Input, Active Low) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Expanded Register File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Stack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Counter/Timer Functional Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Stop Mode Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Watchdog Timer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Low-Voltage Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 20 20 21 25 26 26 35 45 48 49 50 51 57 60
Expanded Register File Control Registers (0D) . . . . . . . . . . . . . . . . . . . . . . 62 Expanded Register File Control Registers (0F) . . . . . . . . . . . . . . . . . . . . . . 69 Standard Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Standard Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 80 81 81 82
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Part Number Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
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Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Customer Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
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Architectural Overview
Maxim's Crimzon(R) ZLR32300 is an ROM-based member of the MCU family of infrared microcontrollers. With 237 B of general-purpose RAM and 4 KB to 32 KB of ROM, CMOS microcontrollers offer fast-executing, efficient use of memory, sophisticated interrupts, input/output (I/O) bit manipulation capabilities, automated pulse generation/reception, and internal key-scan pull-up transistors. The Crimzon ZLR32300 architecture (see Figure 1 on page 4) is based on Maxim's 8-bit microcontroller core with an Expanded Register File allowing access to register-mapped peripherals, I/O circuits, and powerful counter/timer circuitry. The Z8(R) offers a flexible I/O scheme, an efficient register and address space structure, and a number of ancillary features that are useful in many consumer, automotive, computer peripheral, and battery-operated hand-held applications. There are three basic address spaces available to support a wide range of configurations: 1. Program Memory 2. Register File 3. Expanded Register File The register file is composed of 256 bytes of RAM. It includes four I/O port registers, 16 control and status registers, and 236 general-purpose registers. The Expanded Register File consists of two additional register groups (F and D). To unburden the program from coping with such real-time problems as generating complex waveforms or receiving and demodulating complex waveform/pulses, the Crimzon ZLR32300 offers a new intelligent counter/timer architecture with 8-bit and 16-bit counter/timers (see Figure 2 on page 5). Also included are a large number of user-selectable modes and two on-board comparators to process analog signals with separate reference voltages. Note: All signals with an overline, " ", are active Low. For example, B/W, in which WORD is active Low, and B/W, in which BYTE is active Low. Power connections use the conventional descriptions listed in Table 1.
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Crimzon(R) ZLR32300 Product Specification
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Table 1. Power Connections
Connection Power Ground Circuit VCC GND Device VDD VSS
Development Features
Table 2 lists the features of Crimzon ZLR32300 family. Table 2. Crimzon ZLR32300 Family Features
Device Crimzon ZLR32300
*General purpose
ROM (KB)
RAM* (Bytes) I/O Lines
Voltage Range
4, 8, 16, 24, 32 237
32, 24 or 16 2.0-3.6 V
The development features of Crimzon ZLR32300 include:
* *
Low power consumption-5 mW (typical) Three standby modes: - STOP--1.4 A (typical) - HALT--0.5 mA (typical) - Low voltage Special architecture to automate generation and reception of complex pulses or signals: - One programmable 8-bit counter/timer with two capture registers and two load registers - One programmable 16-bit counter/timer with one 16-bit capture register pair and one 16-bit load register pair - Programmable input glitch filter for pulse reception Six priority interrupts - Three external - Two assigned to counter/timers - One low-voltage detection interrupt Low-voltage detection and high-voltage detection Flags Programmable Watchdog Timer/Power-on reset (WDT/POR) circuits Two independent comparators with programmable interrupt polarity
*
*
* * *
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Crimzon(R) ZLR32300 Product Specification
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* *
Mask selectable pull-up transistors on ports 0, 1, 2, 3 ROM options - Port 0: 0-3 pull-up transistors - Port 0: 4-7 pull-up transistors - Port 1: 0-3 pull-up transistors - Port 1: 4-7 pull-up transistors - Port 2: 0-7 pull-up transistors - Port 3: 0-3 pull-up transistors - WDT enabled at POR
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Crimzon(R) ZLR32300 Product Specification
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Functional Block Diagram
Figure 1 displays the ZLR32300 MCU functional block diagram.
P00 P01 P02 P03 I/O Nibble Programmable P04 P05 P06 P07 Register File 256 x 8-Bit Pref1/P30 P31 P32 P33 P34 P35 P36 P37
4
Port 0 4 Register Bus Internal Address Bus ROM Up to 32K x 8 P10 P11 P12 P13 P14 P15 P16 P17 Internal Data Bus 8 Port 1 Expanded Register File Expanded Register Bus
Port 3
Z8(R)Core Z8 Core
I/O Byte Programmable
XTAL Machine Timing & Instruction Control RESET
I/O Bit Programmable
P20 P21 P22 P23 P24 P25 P26 P27
Port 2
Power
VDD VSS
Watchdog Timer
Counter/Timer 8 8-Bit
Counter/Timer 16 16-Bit
Power-On Reset
Low-Voltage Detection
High-Voltage Detection
Note: Refer to the specific package for available pins.
Figure 1. Functional Block Diagram
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Crimzon(R) ZLR32300 Product Specification
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HI16 8
LO16 8
16-Bit T16 1248 8 SCLK Clock Divider TC16H 16 8 TC16L And/OR Logic HI8 8 Input Glitch Filter Edge Detect Circuit 8-Bit T8 8 TC8H 8 TC8L LO8 8
Timer 16
Timer 8/16
Timer 8
Figure 2. Counter/Timers Diagram
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Pin Description
The pin configuration for the 20-pin PDIP/SOIC/SSOP is displayed in Figure 3 and described in Table 3. The pin configuration for the 28-pin PDIP/SOIC/SSOP is displayed in Figure 4 on page 7 and described in Table 4 on page 7. The pin configurations for the 48-pin SSOP versions are displayed in Figure 5 on page 8 and described in Table 5 on page 8.
P25 P26 P27 P07 VDD XTAL2 XTAL1 P31 P32 P33
1 2 3 4 5 6 7 8 9 10
20-Pin PDIP SOIC SSOP
20 19 18 17 16 15 14 13 12 11
P24 P23 P22 P21 P20 VSS P01 P00/Pref1/P30 P36 P34
Figure 3. 20-Pin PDIP/SOIC/SSOP Pin Configuration Table 3. 20-Pin PDIP/SOIC/SSOP Pin Identification
Pin No 1-3 4 5 6 7 8-10 11,12 13 14 15 16-20 Symbol P25-P27 P07 VDD XTAL2 XTAL1 P31-P33 P34, P36 Function Port 2, Bits 5,6,7 Port 0, Bit 7 Power Supply Crystal Oscillator Clock Crystal Oscillator Clock Port 3, Bits 1,2,3 Port 3, Bits 4,6 Output Input Input Output Direction Input/Output Input/Output
P00/Pref1/P30 Port 0, Bit 0/Analog reference input Input/Output for P00 Port 3 Bit 0 Input for Pref1/P30 P01 VSS P20-P24 Port 0, Bit 1 Ground Port 2, Bits 0,1,2,3,4 Input/Output Input/Output
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Crimzon(R) ZLR32300 Product Specification
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P25 P26 P27 P04 P05 P06 P07 VDD XTAL2 XTAL1 P31 P32 P33 P34
1
28
28-Pin PDIP SOIC SSOP
14
15
P24 P23 P22 P21 P20 P03 VSS P02 P01 P00 Pref1/P30 P36 P37 P35
Figure 4. 28-Pin PDIP/SOIC/SSOP Pin Configuration
Table 4.
Pin 1-3 4-7 8 9 10 11-13 14 15 16 17 18 19-21 22 23 24-28
28-Pin PDIP/SOIC/SSOP Pin Identification
Symbol P25-P27 P04-P07 VDD XTAL2 XTAL1 P31-P33 P34 P35 P37 P36 Pref1/P30 Port 3 Bit 0 P00-P02 VSS P03 P20-P24 Direction Input/Output Input/Output Output Input Input Output Output Output Output Input Input/Output Input/Output Input/Output Description Port 2, Bits 5,6,7 Port 0, Bits 4,5,6,7 Power supply Crystal, oscillator clock Crystal, oscillator clock Port 3, Bits 1,2,3 Port 3, Bit 4 Port 3, Bit 5 Port 3, Bit 7 Port 3, Bit 6 Analog ref input; connect to VCC if not used Input for Pref1/P30 Port 0, Bits 0,1,2 Ground Port 0, Bit 3 Port 2, Bits 0-4
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Crimzon(R) ZLR32300 Product Specification
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NC P25 P26 P27 P04 N/C P05 P06 P14 P15 P07 VDD VDD N/C P16 P17 XTAL2 XTAL1 P31 P32 P33 P34 NC VSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
48-Pin SSOP
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
NC NC P24 P23 P22 P21 P20 P03 P13 P12 VSS VSS N/C P02 P11 P10 P01 P00 N/C PREF1/P30 P36 P37 P35 RESET
Figure 5. 48-Pin SSOP Pin Configuration
Table 5. 48-Pin Configuration
48-Pin SSOP No 31 32 35 41 5 7 8 11 33 34 Symbol P00 P01 P02 P03 P04 P05 P06 P07 P10 P11
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Table 5. 48-Pin Configuration (Continued)
48-Pin SSOP No 39 40 9 10 15 16 42 43 44 45 46 2 3 4 19 20 21 22 26 28 27 23 47 1 25 18 17 12, 13 24, 37, 38 29 48 6 Symbol P12 P13 P14 P15 P16 P17 P20 P21 P22 P23 P24 P25 P26 P27 P31 P32 P33 P34 P35 P36 P37 NC NC NC RESET XTAL1 XTAL2 VDD VSS Pref1/P30 NC NC
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Table 5. 48-Pin Configuration (Continued)
48-Pin SSOP No 14 30 36 Symbol NC NC NC
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Pin Functions
XTAL1 Crystal 1 (Time-Based Input)
This pin connects a parallel-resonant crystal or ceramic resonator, to the on-chip oscillator input. Additionally, an optional external single-phase clock can be coded to the on-chip oscillator input.
XTAL2 Crystal 2 (Time-Based Output)
This pin connects a parallel-resonant, crystal or ceramic resonant to the on-chip oscillator output.
Input/Output Ports
Caution: The CMOS input buffer for each Port 0, 1, or 2 pin is always connected to the pin, even when the pin is configured as an output. If the pin is configured as an open-drain output and no external signal is applied, a High output state can cause the CMOS input buffer to float. This might lead to excessive leakage current of more than 100 A. To prevent this leakage, connect the pin to an external signal with a defined logic level or ensure its output state is Low, especially during STOP mode. Internal pull-ups are disabled on any given pin or group of port pins when programmed into output mode. Port 0, 1, and 2 have input and output capability. The input logic is always present no matter whether the port is configured as input or output. When doing a READ instruction, the MCU reads the actual value at the input logic but not from the output buffer. In addition, the instructions of OR, AND, and XOR have the Read-ModifyWrite sequence. The MCU first reads the port, and then modifies the value and load back to the port. Precaution must be taken if the port is configured as opendrain output or if the port is driving any circuit that makes the voltage different from the desired output logic. For example, pins P00-P07 are not connected to anything else. If it is configured as open-drain output with output logic as
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Pin Description
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ONE, it is a floating port and reads back as ZERO. The following instruction sets P00-P07 all LOW.
AND P0,#%F0
Port 0 (P07-P00) Port 0 is an 8-bit, bidirectional, CMOS-compatible port. These eight I/O lines are configured under software control as a nibble I/O port. The output drivers are push-pull or open-drain controlled by bit D2 in the PCON register. If one or both nibbles are needed for I/O operation, they must be configured by writing to the Port 0 mode register. After a hardware reset, Port 0 is configured as an input port. An optional pull-up transistor is available as a mask option on all Port 0 bits with nibble select.
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Pin Description
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Note:
The Port 0 direction is reset to be input following an Stop Mode Recovery.
4 ZLR32300 ROM Port 0 (I/O) 4
Open-Drain I/O
Mask VCC Option Resistive Transistor Pull-up Pad
Out
In
Figure 6.
Port 0 Configuration
Port 1 (P17-P10) Port 1 (see Figure 7) can be configured for standard port input or output mode. After POR, Port 1 is configured as an input port. The output drivers are either push-pull or open-drain and are controlled by bit D1 in the PCON register.
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Pin Description
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14
Note:
The Port 1 direction is reset to be input following an SMR. In 20- and 28-pin packages, Port 1 is reserved. A write to this register will have no effect and will always read FF.
ZLR32300 ROM
8
Port 1 (I/O)
Open-Drain OEN
Mask Option
VCC Resistive Transistor Pull-up Pad
Out
In
Figure 7.
Port 1 Configuration
Port 2 (P27-P20) Port 2 is an 8-bit, bidirectional, CMOS-compatible I/O port (see Figure 8 on page 15). These eight I/O lines can be independently configured under software control as inputs or outputs. Port 2 is always available for I/O operation. A mask option is available to connect eight pull-up transistors on this port. Bits programmed as outputs are globally programmed as either push-pull or open-drain. The POR resets with the eight bits of Port 2 configured as inputs.
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Pin Description
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Port 2 also has an 8-bit input OR and AND gate, which can be used to wake up the part. P20 can be programmed to access the edge-detection circuitry in DEMODULATION mode.
ZLR32300 ROM
Port 2 (I/O)
Open-Drain I/O
Mask VCC Option Resistive Transistor Pull-up Pad
Out
In
Figure 8.
Port 2 Configuration
Port 3 (P37-P30) Port 3 is a 8-bit, CMOS-compatible fixed I/O port (see Figure 9 on page 16). Port 3 consists of four fixed input (P33-P30) and four fixed output (P37-P34), which can be configured under software control for interrupt and as output from the counter/ timers. P30, P31, P32, and P33 are standard CMOS inputs; P34, P35, P36, and P37 are push-pull outputs.
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Pref1/P30 P31 P32 P33 ZLR32300 ROM P34 P35 P36 P37 Port 3 (I/O)
R247 = P3M D1 1 = Analog 0 = Digital
P31 (AN1) Pref1 + Comp1
Dig. IRQ2, P31 Data Latch An.
P32 (AN2) P33 (REF2) + Comp2
IRQ0, P32 Data Latch
From Stop Mode Recovery Source of SMR
IRQ1, P33 Data Latch
Figure 9. Port 3 Configuration Two on-board comparators process analog signals on P31 and P32, with reference to the voltage on Pref1 and P33. The Analog function is enabled by programming the Port 3 Mode Register (bit 1). P31 and P32 are programmable as rising, falling, or both edge triggered interrupts (IRQ register bits 6 and 7). Pref1 and P33 are the comparator reference voltage inputs. Access to the Counter Timer edge-detection circuit is through P31 or P20 (see T8 and T16 Common Func-
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Pin Description
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tions--CTR1(0D)01h on page 30). Other edge detect and IRQ modes are described in Table 6. Note: Comparators are powered down by entering STOP mode. For P31-P33 to be used in a SMR source, these inputs must be placed into DIGITAL mode.
2
Table 6. Port 3 Pin Function Summary
Pin Pref1/P30 P31 P32 P33 P34 P35 P36 P37 P20 I/O IN IN IN IN OUT OUT OUT OUT I/O IN T8 T16 T8/16 AO2 IN Counter/Timers Comparator Interrupt RF1 AN1 AN2 RF2 AO1 IRQ2 IRQ0 IRQ1
Port 3 also provides output for each of the counter/timers and the AND/OR Logic (see Figure 10 on page 18). Control is performed by programming bits D5-D4 of CTR1, bit 0 of CTR0, and bit 0 of CTR2.
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Pin Description
Crimzon(R) ZLR32300 Product Specification
18
CTR0, D0
P34 data
PCON, D0
MUX
T8_Out
VDD Pad P34
MUX P3M D1 P31 P31 P30 (Pref1) + Comp1
CTR2, D0
VDD Pad P35
Out 35 T16_Out
MUX
CTR1, D6 Out 36 T8/T16_Out
VDD Pad P36
MUX
PCON, D0
P37 data
VDD Pad P37
MUX
P3M D1 P32 P32 P33 + Comp2
Figure 10. Port 3 Counter/Timer Output Configuration
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Pin Description
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Comparator Inputs In ANALOG mode, P31 and P32 have a comparator front end. The comparator reference is supplied to P33 and Pref1. In this mode, the P33 internal data latch and its corresponding IRQ1 are diverted to the SMR sources (excluding P31, P32, and P33) as displayed in Figure 9 on page 16. In DIGITAL mode, P33 is used as D3 of the Port 3 input register, which then generates IRQ1. Note: Comparators are powered down by entering STOP mode. For P31-P33 to be used in a SMR source, these inputs must be placed into DIGITAL mode. Comparator Outputs These channels can be programmed to be output on P34 and P37 through the PCON register.
RESET (Input, Active Low)
Reset initializes the MCU and is accomplished either through Power-On, Watchdog Timer, Stop Mode Recovery, Low-Voltage detection, or external reset. During Power-On Reset and Watchdog Timer Reset, the internally generated reset drives the reset pin Low for the POR time. Any devices driving the external reset line must be open-drain to avoid damage from a possible conflict during reset conditions. Pull-up is provided internally. When the ZLR32300 asserts (Low) the RESET pin, the internal pull-up is disabled. The ZLR32300 does not assert the RESET pin when under VBO. Note: The external Reset does not initiate an exit from STOP mode.
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Functional Description
This device incorporates special functions to enhance the Z8(R) functionality in consumer and battery-operated applications.
Program Memory
This device addresses 32 KB of ROM memory. The first 12 bytes are reserved for interrupt vectors. These locations contain the six 16-bit vectors that correspond to the six available interrupts (see Figure 11on page 21).
RAM
This device features 256 B of RAM.
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Functional Description
Crimzon(R) ZLR32300 Product Specification
21
Location of first byte of instruction executed after RESET
32768
Not Accessible On-Chip ROM
12 11 10 9 8 7
Reset Start Address IRQ5 IRQ5 IRQ4 IRQ4 IRQ3 IRQ3 IRQ2 IRQ2 IRQ1 IRQ1 IRQ0 IRQ0
Interrupt Vector (Lower Byte)
6 5
4 Interrupt Vector (Upper Byte) 3 2 1
0
Figure 11.Program Memory Map (32 K ROM)
Expanded Register File
The register file has been expanded to allow for additional system control registers and for mapping of additional peripheral devices into the register address area. The Z8 register address space (R0 through R15) has been implemented as 16 banks, with 16 registers per bank. These register groups are known as the
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Functional Description
Crimzon(R) ZLR32300 Product Specification
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ERF (Expanded Register File). Bits 7-4 of register RP select the working register group. Bits 3-0 of register RP select the expanded register file bank. Note: An expanded register bank is also referred to as an expanded register group (see Figure 12 on page 23).
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Functional Description
Crimzon(R) ZLR32300 Product Specification
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Z8(R) Standard Control Registers
FF FE SPL SPH RP FLAGS IMR IRQ IPR P01M P3M P2M Reserved Reserved Reserved Reserved Reserved Reserved
Reset Condition
Expanded Reg. Bank 0/Group 15** D7 D6 D5 D4 D3 D2 D1 D0 UUUUUUUU UUUUUUUU 00000000 UUUUUUUU UUUUUUUU 00000000 UUUUUUUU 11001111 00000000 11111111 UUUUUUUU UUUUUUUU UUUUUUUU UUUUUUUU UUUUUUUU UUUUUUUU
Register Pointer
76543210 Working Register Group Pointer Expanded Register Bank Pointer * *
FD FC FB FA F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
Register File (Bank 0)** FF F0
Expanded Reg. Bank F/Group 0** * * (F) 0F WDTMR (F) 0E Reserved (F) 0D SMR2 (F) 0C Reserved 7F (F) 0B SMR (F) 0A Reserved (F) 09 Reserved (F) 08 Reserved (F) 07 Reserved (F) 06 Reserved (F) 05 Reserved 0F 00 (F) 04 Reserved (F) 03 Reserved (F) 02 Reserved (F) 01 Reserved Expanded Reg. Bank 0/Group (0) (0) 03 P3 (0) 02 P2 * (0) 01 P1 (0) 00 P0 U = Unknown * Not reset with a Stop Mode Recovery. P1 reserved in 20 and 28-pin package. ** All addresses are in hexadecimal Is not reset with a Stop Mode Recovery, except Bit 0 Bit 5 Is not reset with a Stop Mode Recovery Bits 5,4,3,2 not reset with a Stop Mode Recovery Bits 5 and 4 not reset with a Stop Mode Recovery Bits 5,4,3,2,1 not reset with a Stop Mode Recovery 0 U U U U * (F) 00 PCON 11111110 U01000U0 00000000 UU001101
Expanded Reg. Bank D/Group 0 (D) 0C * * * * * * * * (D) 0B (D) 0A (D) 09 (D) 08 (D) 07 (D) 06 (D) 05 (D) 04 (D) 03 (D) 02 (D) 01 (D) 00 LVD HI8 LO8 HI16 LO16 TC16H TC16L TC8H TC8L CTR3 CTR2 CTR1 CTR0 UUUUUUU0 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00011111 00000000 00000000 00000000
Figure 12. Expanded Register File Architecture
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Crimzon(R) ZLR32300 Product Specification
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The upper nibble of the register pointer (see Figure 13) selects which working register group of 16 bytes in the register file, is accessed out of the possible 256. The lower nibble selects the expanded register file bank and, in the case of the Crimzon ZLR32300 family, banks 0, F, and D are implemented. A 0h in the lower nibble allows the normal register file (bank 0) to be addressed. Any other value from 1h to Fh exchanges the lower 16 registers to an expanded register bank.
R253 RP D7 D6 D5 D4 D3 D2 D1 D0
Expanded Register File Pointer Working Register Pointer
Default Setting After Reset = 0000 0000
Figure 13. Register Pointer Example: Crimzon ZLR32300 (see Figure 12 on page 23). R253 RP = 00h R0 = Port 0 R1 = Port 1 R2 = Port 2 R3 = Port 3 But if: R253 RP = 0Dh R0 = CTR0 R1 = CTR1 R2 = CTR2 R3 = CTR3 The counter/timers are mapped into ERF group D. Access is easily performed using the following:
LD for access to bank D register group 0) LD LD RP, #0Dh ; Select ERF D ; (working R0,#xx 1, #xx ; load CTR0 ; load CTR1
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LD LD for access to bank D
R1, 2 RP, #0Dh
; CTR2CTR1 ; Select ERF D ; (working
register group 0) LD RP, #7Dh expanded register bank D and working group 7 of bank 0 for access. LD 71h, 2 ; CTR2register 71h LD R1, 2 ; CTR2register 71h
; Select ; register
Register File
The register file (bank 0) consists of 4 I/O port registers, 237 general-purpose registers, 16 control and status registers (R0-R3, R4-R239, and R240-R255, respectively), and two expanded registers groups in Banks D (see Table 7 on page 28) and F. Instructions can access registers directly or indirectly through an 8-bit address field, thereby allowing a short, 4-bit register address to use the Register Pointer (see Figure 14 on page 26). In the 4-bit mode, the register file is divided into 16 working register groups, each occupying 16 continuous locations. The Register Pointer addresses the starting location of the active working register group.
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Note:
Working register group E0-EF can only be accessed through working registers and indirect addressing modes.
R7 R6 R5 R4
R3 R2 R1 R0
R253
The upper nibble of the register file address provided by the register pointer specifies the active working-register group.
FF F0 EF E0 DF D0 40 3F 30 2F 20 1F Register Group 1 10 0F 00 Register Group 0 I/O Ports
Specified Working Register Group Register Group 2
The lower nibble of the register file address provided by the instruction points to the specified register. R15 to R0 R15 to R4 * R3 to R0 *
* RP = 00: Selects Register Bank 0, Working Register Group 0
Figure 14. Register Pointer--Detail
Stack
The internal register file is used for the stack. An 8-bit Stack Pointer SPL (R255) is used for the internal stack that resides in the general-purpose registers (R4- R239). SPH (R254) can be used as a general-purpose register.
Timers
T8_Capture_HI--HI8(D)0BH This register holds the captured data from the output of the 8-bit Counter/Timer0. Typically, this register holds the number of counts when the input signal is 1.
Field T8_Capture_HI Bit Position [7:0] R/W Description Captured Data--No Effect
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T8_Capture_LO--L08(D)0AH This register holds the captured data from the output of the 8-bit Counter/Timer0. Typically, this register holds the number of counts when the input signal is 0.
Field T8_Capture_L0 Bit Position [7:0] R/W Description Captured Data--No Effect
T16_Capture_HI--HI16(D)09H This register holds the captured data from the output of the 16-bit Counter/ Timer16. This register holds the MS-Byte of the data.
Field Bit Position R/W Description Captured Data--No Effect
T16_Capture_HI [7:0]
T16_Capture_LO--L016(D)08H This register holds the captured data from the output of the 16-bit Counter/ Timer16. This register holds the LS-Byte of the data.
Field Bit Position Description R/W Captured Data--No Effect
T16_Capture_LO [7:0]
Counter/Timer2 MS-Byte Hold Register--TC16H(D)07H
Field T16_Data_HI Bit Position [7:0] R/W Description Data
Counter/Timer2 LS-Byte Hold Register--TC16L(D)06H
Field T16_Data_LO Bit Position [7:0] R/W Description Data
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Counter/Timer8 High Hold Register--TC8H(D)05H
Field T8_Level_HI Bit Position [7:0] R/W Description Data
Counter/Timer8 Low Hold Register--TC8L(D)04H
Field T8_Level_LO Bit Position [7:0] R/W Description Data
CTR0 Counter/Timer8 Control Register--CTR0(D)00H Table 7 lists and briefly describes the fields for this register. Table 7. CTR0(D)00H Counter/Timer8 Control Register
Field T8_Enable Bit Position 7------R/W Value 0* 1 0 1 0* 1 0** 1 0 1 0 0** 01 10 11 0** 1 0** 1 0* 1 Description Counter Disabled Counter Enabled Stop Counter Enable Counter Modulo-N Single Pass No Counter Time-Out Counter Time-Out Occurred No Effect Reset Flag to 0 SCLK SCLK/2 SCLK/4 SCLK/8 Disable Data Capture Interrupt Enable Data Capture Interrupt Disable Time-Out Interrupt Enable Time-Out Interrupt P34 as Port Output T8 Output on P34
Single/Modulo-N Time_Out
-6--------5------
R/W R/W
T8 _Clock
---43---
R/W
Capture_INT_Mask Counter_INT_Mask P34_Out
-----2-------1-------0
R/W R/W R/W
*Indicates the value upon Power-on reset. **Indicates the value upon Power-on reset. Not reset with a Stop Mode Recovery.
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T8 Enable This field enables T8 when set (written) to 1. Single/Modulo-N When set to 0 (Modulo-N), the counter reloads the initial value when the terminal count is reached. When set to 1 (single-pass), the counter stops when the terminal count is reached. Timeout This bit is set when T8 times out (terminal count reached). To reset this bit, write a 1 to its location. Caution: Writing a 1 is the only way to reset the Terminal Count status condition. Reset this bit before using/enabling the counter/timers. The first clock of T8 might not have complete clock width and can occur any time when enabled. Note: Ensure to manipulate CTR0, bit 5 and CTR1, bits 0 and 1 (DEMODULATION mode) when using the OR or AND commands. These instructions use a Read-Modify-Write sequence in which the current status from the CTR0 and CTR1 registers is ORed or ANDed with the designated value and then written back into the registers. T8 Clock These bits define the frequency of the input signal to T8.
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Capture_INT_Mask Set this bit to allow an interrupt when data is captured into either LO8 or HI8 upon a positive or negative edge detection in DEMODULATION mode. Counter_INT_Mask Set this bit to allow an interrupt when T8 has a timeout. P34_Out This bit defines whether P34 is used as a normal output pin or the T8 output. T8 and T16 Common Functions--CTR1(0D)01h This register controls the functions in common with the T8 and T16. Table 8 lists and briefly describes the fields for this register.
Table 8. CTR1(0D)01H T8 and T16 Common Functions
Field Mode P36_Out/ Demodulator_Input Bit Position 7-------6-----R/W R/W 0* 1 0* 1 T8/T16_Logic/ Edge _Detect --54---R/W 00** 01 10 11 00** 01 10 11 Value 0* 1 Description TRANSMIT mode DEMODULATION mode TRANSMIT mode Port Output T8/T16 Output DEMODULATION mode P31 P20 TRANSMIT mode AND OR NOR NAND DEMODULATION mode Falling Edge Rising Edge Both Edges Reserved
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Table 8. CTR1(0D)01H T8 and T16 Common Functions (Continued)
Field Transmit_Submode/ Glitch_Filter Bit Position ----32-Value R/W 00 01 10 11 00 01 10 11 Initial_T8_Out/ Rising Edge ------1R/W 0 1 0 1 0 1 0 1 0 1 0 1 Description TRANSMIT mode Normal Operation PING-PONG mode T16_Out = 0 T16_Out = 1 DEMODULATION mode No Filter 4 SCLK Cycle 8 SCLK Cycle Reserved TRANSMIT mode T8_OUT is 0 Initially T8_OUT is 1 Initially DEMODULATION mode No Rising Edge Rising Edge Detected No Effect Reset Flag to 0 TRANSMIT mode T16_OUT is 0 Initially T16_OUT is 1 Initially DEMODULATION mode No Falling Edge Falling Edge Detected No Effect Reset Flag to 0
R W Initial_T16_Out/ Falling_Edge -------0 R/W
R W
*Default at Power-On Reset. **Default at Power-On Reset. Not reset with a Stop Mode Recovery.
Mode If the result is 0, the counter/timers are in TRANSMIT mode; otherwise, they are in DEMODULATION mode. P36_Out/Demodulator_Input In TRANSMIT mode, this bit defines whether P36 is used as a normal output pin or the combined output of T8 and T16. In DEMODULATION mode, this bit defines whether the input signal to the Counter/Timers is from P20 or P31. If the input signal is from Port 31, a capture event may also generate an IRQ2 interrupt. To prevent generating an IRQ2, either disable the IRQ2 interrupt by clearing its IMR bit D2 or use P20 as the input.
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T8/T16_Logic/Edge _Detect In TRANSMIT mode, this field defines how the outputs of T8 and T16 are combined (AND, OR, NOR, NAND). In DEMODULATION mode, this field defines which edge should be detected by the edge detector. Transmit_Submode/Glitch Filter In TRANSMIT mode, this field defines whether T8 and T16 are in the PING-PONG mode or in independent normal operation mode. Setting this field to `NORMAL OPERATION mode' terminates the `PING-PONG mode' operation. When set to 10, T16 is immediately forced to a 0; a setting of 11 forces T16 to output a 1. In DEMODULATION mode, this field defines the width of the glitch that must be filtered out. Initial_T8_Out/Rising_Edge In TRANSMIT mode, if 0, the output of T8 is set to 0 when it starts to count. If 1, the output of T8 is set to 1 when it starts to count. When the counter is not enabled and this bit is set to 1 or 0, T8_OUT is set to the opposite state of this bit. This ensures that when the clock is enabled, a transition occurs to the initial state set by CTR1, D1. In DEMODULATION mode, this bit is set to 1 when a rising edge is detected in the input signal. In order to reset the mode, a 1 should be written to this location. Initial_T16 Out/Falling _Edge In TRANSMIT mode, if it is 0, the output of T16 is set to 0 when it starts to count. If it is 1, the output of T16 is set to 1 when it starts to count. This bit is effective only in Normal or PING-PONG mode (CTR1, D3; D2). When the counter is not enabled and this bit is set, T16_OUT is set to the opposite state of this bit. This ensures that when the clock is enabled, a transition occurs to the initial state set by CTR1, D0. In DEMODULATION mode, this bit is set to 1 when a falling edge is detected in the input signal. In order to reset it, a 1 must be written to this location. Note: Modifying CTR1 (D1 or D0) while the counters are enabled causes unpredictable output from T8/16_OUT. CTR2 Counter/Timer 16 Control Register--CTR2(D)02H Table 9 on page 33 lists and briefly describes the fields for this register.
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Table 9. CTR2(D)02H: Counter/Timer16 Control Register
Field T16_Enable Bit Position 7------R W Single/Modulo-N -6-----R/W 0* 1 0 1 Time_Out --5----R 0** 1 0 1 00** 01 10 11 0** 1 0* 1 0* 1 Value 0* 1 0 1 Description Counter Disabled Counter Enabled Stop Counter Enable Counter TRANSMIT mode Modulo-N Single Pass DEMODULATION mode T16 Recognizes Edge T16 Does Not Recognize Edge No Counter Timeout Counter Timeout Occurred No Effect Reset Flag to 0 SCLK SCLK/2 SCLK/4 SCLK/8 Disable Data Capture Int. Enable Data Capture Int. Disable Timeout Int. Enable Timeout Int. P35 as Port Output T16 Output on P35
W T16 _Clock ---43--R/W
Capture_INT_Mask Counter_INT_Mask P35_Out
-----2-------1-------0
R/W R/W R/W
*Indicates the value upon Power-On Reset. **Indicates the value upon Power-On Reset. Not reset with a Stop Mode Recovery.
T16_Enable This field enables T16 when set to 1. Single/Modulo-N In TRANSMIT mode, when set to 0, the counter reloads the initial value when it reaches the terminal count. When set to 1, the counter stops when the terminal count is reached.
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In DEMODULATION mode, when set to 0, T16 captures and reloads on detection of all the edges. When set to 1, T16 captures and detects on the first edge but ignores the subsequent edges. For details, see the description of T16 DEMODULATION mode on page 42. Time_Out This bit is set when T16 times out (terminal count reached). To reset the bit, write a 1 to this location. T16_Clock This bit defines the frequency of the input signal to Counter/Timer16. Capture_INT_Mask This bit is set to allow an interrupt when data is captured into LO16 and HI16. Counter_INT_Mask Set this bit to allow an interrupt when T16 times out. P35_Out This bit defines whether P35 is used as a normal output pin or T16 output. CTR3 T8/T16 Control Register--CTR3(D)03H Table 10 lists and briefly describes the fields for this register. This register allows the T8 and T16 counters to be synchronized. Table 10. CTR3 (D)03H: T8/T16 Control Register
Field T16 Enable Bit Position 7------R R W W R R W W R/W Value 0** 1 0 1 0** 1 0 1 0* 1 Description Counter Disabled Counter Enabled Stop Counter Enable Counter Counter Disabled Counter Enabled Stop Counter Enable Counter Disable Sync Mode Enable Sync Mode
T8 Enable
-6------
Sync Mode
--5-----
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Table 10. CTR3 (D)03H: T8/T16 Control Register (Continued)
Field Reserved Bit Position ---43210 R W Value 1 x Description Always reads 11111 No Effect
*Indicates the value upon Power-On Reset. **Indicates the value upon Power-On Reset. Not reset with a Stop Mode Recovery.
Counter/Timer Functional Blocks
Input Circuit The edge detector monitors the input signal on P31 or P20. Based on CTR1 D5- D4, a pulse is generated at the Pos Edge or Neg Edge line when an edge is detected. Glitches in the input signal that have a width less than specified (CTR1 D3, D2) are filtered out (see Figure 15).
CTR1 D5,D4 P31 MUX P20 Glitch Filter Edge Detector Pos Edge Neg Edge
CTR1 D6
CTR1 D3, D2
Figure 15.Glitch Filter Circuitry T8 TRANSMIT Mode Before T8 is enabled, the output of T8 depends on CTR1, D1. If it is 0, T8_OUT is 1; if it is 1, T8_OUT is 0 (see Figure 16 on page 36).
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T8 (8-Bit) Transmit Mode
No
T8_Enable Bit Set CTR0, D7 Yes
Reset T8_Enable Bit 0 Load TC8L Reset T8_OUT
CTR1, D1 Value
1 Load TC8H Set T8_OUT
Set Timeout Status Bit (CTR0 D5) and Generate Timeout_Int if Enabled
Enable T8
No
T8_Timeout Yes
Single Pass
Single Pass? Modulo-N
1 Load TC8L Reset T8_OUT
T8_OUT Value
0 Load TC8H Set T8_OUT
Enable T8
Set Timeout Status Bit (CTR0 D5) and Generate Timeout_Int if Enabled
No
T8_Timeout Yes
Figure 16.TRANSMIT Mode Flowchart
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When T8 is enabled, the output T8_OUT switches to the initial value (CTR1, D1). If the initial value (CTR1, D1) is 0, TC8L is loaded; otherwise, TC8H is loaded into the counter. In SINGLE-PASS mode (CTR0, D6), T8 counts down to 0 and stops, T8_OUT toggles, the timeout status bit (CTR0, D5) is set, and a timeout interrupt can be generated if it is enabled (CTR0, D1). In MODULO-N mode, upon reaching terminal count, T8_OUT is toggled, but no interrupt is generated. From that point, T8 loads a new count (if the T8_OUT level now is 0), TC8L is loaded; if it is 1, TC8H is loaded. T8 counts down to 0, toggles T8_OUT, and sets the timeout status bit (CTR0, D5), thereby generating an interrupt if enabled (CTR0, D1). One cycle is thus completed. T8 then loads from TC8H or TC8L according to the T8_OUT level and repeats the cycle. See Figure 17.
Z8 Data Bus Positive Edge Negative Edge HI8 LO8 CTR0 D1 IRQ4 CTR0 D2
CTR0 D4, D3 Clock Select Clock 8-Bit Counter T8
SCLK
T8_OUT
TC8H Z8 Data Bus
TC8L
Figure 17.8-Bit Counter/Timer Circuits You can modify the values in TC8H or TC8L at any time. The new values take effect when they are loaded. Caution: To ensure known operation do not write these registers at the time the values are to be loaded into the counter/timer.
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An initial count of 1 is not allowed (a non-function occurs). An initial count of 0 causes TC8 to count from 0 to FFH to FEH. Note: The letter H denotes hexadecimal values. Transition from 0 to FFH is not a timeout condition. Caution: Using the same instructions for stopping the counter/timers and setting the status bits is not recommended.
Two successive commands are necessary. First, the counter/timers must be stopped. Second, the status bits must be reset. These commands are required because it takes one counter/timer clock interval for the initiated event to actually occur. See Figure 18 and Figure 19.
TC8H Counts
Counter Enable Command; T8_OUT Switches to Its Initial Value (CTR1 D1)
T8_OUT Toggles; Timeout Interrupt
Figure 18. T8_OUT in SINGLE-PASS Mode
T8_OUT Toggles ... T8_OUT TC8L TC8H TC8L TC8H TC8L
Counter Enable Command; T8_OUT Switches to Its Initial Value (CTR1 D1)
Timeout Interrupt
Timeout Interrupt
Figure 19. T8_OUT in MODULO-N Mode
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T8 DEMODULATION Mode You must program TC8L and TC8H to FFh. After T8 is enabled, when the first edge (rising, falling, or both depending on CTR1, D5; D4) is detected, it starts to count down. When a subsequent edge (rising, falling, or both depending on CTR1, D5; D4) is detected during counting, the current value of T8 is complemented and put into one of the capture registers. If it is a positive edge, data is put into LO8; if it is a negative edge, data is put into HI8. From that point, one of the edge detect status bits (CTR1, D1; D0) is set, and an interrupt can be generated if enabled (CTR0, D2). Meanwhile, T8 is loaded with FFh and starts counting again. If T8 reaches 0, the timeout status bit (CTR0, D5) is set, and an interrupt can be generated if enabled (CTR0, D1). T8 then continues counting from FFh (see Figure 20 and Figure 21).
T8 (8-Bit) Count Capture
No
T8 Enable (Set by User) Yes
No
Edge Present Yes
What Kind of Edge Positive Negative
T8 LO8
T8 HI8
FFh T8
Figure 20.DEMODULATION Mode Count Capture Flowchart
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T8 (8-Bit) Demodulation Mode
No
T8 Enable CTR0, D7 Yes FFh TC8
No
First Edge Present Yes
Disable TC8
Enable TC8
No
T8_Enable Bit Set Yes Edge Present Yes No No T8 Timeout Yes
Set Edge Present Status Bit and Trigger Data Capture Int. If Enabled
Set Timeout Status Bit and Trigger Timeout Int. If Enabled Continue Counting
Figure 21. DEMODULATION Mode Flowchart
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T16 TRANSMIT Mode In NORMAL or PING-PONG mode, the output of T16 when not enabled, is dependent on CTR1, D0. If it is a 0, T16_OUT is a 1; if it is a 1, T16_OUT is 0. You can force the output of T16 to either a 0 or 1 whether it is enabled or not by programming CTR1 D3; D2 to a 10 or 11. When T16 is enabled, TC16H * 256 + TC16L is loaded, and T16_OUT is switched to its initial value (CTR1, D0). When T16 counts down to 0, T16_OUT is toggled (in NORMAL or PING-PONG mode), an interrupt (CTR2, D1) is generated (if enabled), and a status bit (CTR2, D5) is set (see Figure 22).
Z8 Data Bus Positive Edge Negative Edge HI16 LO16 CTR2 D1 IRQ3 CTR2 D2
CTR2 D4, D3 Clock Select Clock 16-Bit Counter T16
SCLK
T16_OUT
TC16H Z8 Data Bus
TC16L
Figure 22.16-Bit Counter/Timer Circuits Note: Global interrupts override this function as described in Interrupts on page 45. If T16 is in SINGLE-PASS mode, it is stopped at this point (see Figure 23 on page 42). If it is in MODULO-N mode, it is loaded with TC16H * 256 + TC16L, and the counting continues (see Figure 24 on page 42). You can modify the values in TC16H and TC16L at any time. The new values take effect when they are loaded.
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Caution:
Do not load these registers at the time the values are to be loaded into the counter/timer to ensure known operation. An initial count of 1 is not allowed. An initial count of 0 causes T16 to count from 0 to FFFFH to FFFEH. Transition from 0 to FFFFH is not a timeout condition.
TC16H*256+TC16L Counts
"Counter Enable" Command T16_OUT Switches to Its Initial Value (CTR1 D0)
T16_OUT Toggles, Timeout Interrupt
Figure 23.T16_OUT in SINGLE-PASS Mode
TC16H*256+TC16L TC16_OUT TC16H*256+TC16L
TC16H*256+TC16L ...
"Counter Enable" Command, T16_OUT Switches to Its Initial Value (CTR1 D0)
T16_OUT Toggles, Timeout Interrupt
T16_OUT Toggles, Timeout Interrupt
Figure 24.T16_OUT in Modulo-N Mode T16 DEMODULATION Mode You must program TC16L and TC16H to FFH. After T16 is enabled, and the first edge (rising, falling, or both depending on CTR1 D5; D4) is detected, T16 captures HI16 and LO16, reloads, and begins counting. If D6 of CTR2 Is 0 When a subsequent edge (rising, falling, or both depending on CTR1, D5; D4) is detected during counting, the current count in T16 is complemented and put into HI16 and LO16. When data is captured, one of the edge detect status bits (CTR1, D1; D0) is set and an interrupt is generated if enabled (CTR2, D2). T16 is loaded with FFFFH and starts again.
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This T16 mode is generally used to measure space time, the length of time between bursts of carrier signal (marks). If D6 of CTR2 Is 1 T16 ignores the subsequent edges in the input signal and continues counting down. A timeout of T8 causes T16 to capture its current value and generate an interrupt if enabled (CTR2, D2). In this case, T16 does not reload and continues counting. If the D6 bit of CTR2 is toggled (by writing a 0 then a 1 to it), T16 captures and reloads on the next edge (rising, falling, or both depending on CTR1, D5; D4), continuing to ignore subsequent edges. This T16 mode generally measures mark time, the length of an active carrier signal burst. If T16 reaches 0, T16 continues counting from FFFFH. Meanwhile, a status bit (CTR2 D5) is set, and an interrupt timeout can be generated if enabled (CTR2 D1). PING-PONG Mode This operation mode is only valid in TRANSMIT mode. T8 and T16 must be programmed in SINGLE-PASS mode (CTR0, D6; CTR2, D6), and PING-PONG mode must be programmed in CTR1, D3; D2. You can begin the operation by enabling either T8 or T16 (CTR0, D7 or CTR2, D7). For example, if T8 is enabled, T8_OUT is set to this initial value (CTR1, D1). According to T8_OUT's level, TC8H or TC8L is loaded into T8. After the terminal count is reached, T8 is disabled, and T16 is enabled. T16_OUT then switches to its initial value (CTR1, D0), data from TC16H and TC16L is loaded, and T16 starts to count. After T16 reaches the terminal count, it stops, T8 is enabled again, repeating the entire cycle. Interrupts can be allowed when T8 or T16 reaches terminal control (CTR0, D1; CTR2, D1). To stop the ping-pong operation, write 00 to bits D3 and D2 of CTR1. See Figure 25. Note: Enabling Ping-Pong operation while the counter/timers are running might cause intermittent counter/timer function. Disable
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the counter/timers and reset the Status Flags before instituting this operation.
Enable TC8 Enable
Timeout Ping-Pong CTR1 D3,D2
TC16
Timeout
Figure 25.PING-PONG Mode Diagram Initiating PING-PONG Mode First, make sure both counter/timers are not running. Set T8 into SINGLE-PASS mode (CTR0, D6), set T16 into SINGLE-PASS mode (CTR2, D6), and set the PING-PONG mode (CTR1, D2; D3). These instructions can be in random order. Finally, start PING-PONG mode by enabling either T8 (CTR0, D7) or T16 (CTR2, D7). See Figure 26.
P34_Internal MUX P34
CTR0 D0 T8_OUT T16_OUT CTR1, D2 CTR1 D5, D4 CTR1 D3 CTR2 D0 P35_Internal P36_Internal AND/OR/NOR/NAND Logic MUX CTR1 D6 MUX P35 P36
MUX
Figure 26.Output Circuit The initial value of T8 or T16 must not be 1. If you stop the timer and restart the timer, reload the initial value to avoid an unknown previous value.
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During PING-PONG Mode The enable bits of T8 and T16 (CTR0, D7; CTR2, D7) are set and cleared alternately by hardware. The timeout bits (CTR0, D5; CTR2, D5) are set every time the counter/timers reach the terminal count. Timer Output The output logic for the timers is displayed in Figure 26 on page 44. P34 is used to output T8-OUT when D0 of CTR0 is set. P35 is used to output the value of TI6OUT when D0 of CTR2 is set. When D6 of CTR1 is set, P36 outputs the logic combination of T8-OUT and T16-OUT determined by D5 and D4 of CTR1.
Interrupts
The Crimzon ZLR32300 features six different interrupts (see Table 11on page 47). The interrupts are maskable and prioritized (see Figure 27 on page 46). The six sources are divided as follows: three sources are claimed by Port 3 lines P33- P31, two by the counter/timers (see Table 11 on page 47) and one for Low-Voltage detection. The Interrupt Mask Register (globally or individually) enables or disables the six interrupt requests. The source for IRQ is determined by bit 1 of the Port 3 mode register (P3M). In DIGITAL mode, Pin P33 is the source. In ANALOG mode the output of the Stop Mode Recovery source logic is used as the source for the interrupt. See Figure 32 on page 54.
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P33 0
Stop Mode Recovery Source 1 D1 of P3M Register
P31
P32
IRQ Register D6, D7
Interrupt Edge Select IRQ2 IRQ0 IRQ1
Timer 16 IRQ3
Timer 8
Low-Voltage Detection IRQ5
IRQ4
IRQ
IMR
5
IPR Global Interrupt Enable Interrupt Request Priority Logic Vector Select
Figure 27. Interrupt Block Diagram
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Table 11. Interrupt Types, Sources, and Vectors
Name IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 Source P32 P33 P31, TIN T16 T8 LVD Vector Location Comments 0,1 2,3 4,5 6,7 8,9 10,11 External (P32), Rising, Falling Edge Triggered External (P33), Falling Edge Triggered External (P31), Rising, Falling Edge Triggered Internal Internal Internal
When more than one interrupt is pending, priorities are resolved by a programmable priority encoder controlled by the Interrupt Priority Register. An interrupt machine cycle activates when an interrupt request is granted. As a result, all subsequent interrupts are disabled, and the Program Counter and Status Flags are saved. The cycle then branches to the Program Memory vector location reserved for that interrupt. All Crimzon ZLR32300 interrupts are vectored through locations in the Program Memory. This memory location and the next byte contain the 16-bit address of the interrupt service routine for that particular interrupt request. To accommodate polled interrupt systems, interrupt inputs are masked, and the Interrupt Request register is polled to determine which of the interrupt requests require service. An interrupt resulting from AN1 is mapped into IRQ2, and an interrupt from AN2 is mapped into IRQ0. Interrupts IRQ2 and IRQ0 can be rising, falling, or both edge triggered. You can program these interrupts. The software can poll to identify the state of the pin. Programming bits for the Interrupt Edge Select are located in the IRQ Register (R250), bits D7 and D6. The configuration is indicated in Table 12. Table 12.IRQ Register
IRQ D7 0 0 1 1 D6 0 1 0 1 Interrupt Edge IRQ2 (P31) F F R R/F IRQ0 (P32) F R F R/F
Note: F = Falling Edge; R = Rising Edge
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Clock
The device's on-chip oscillator has a high-gain, parallel-resonant amplifier, for connection to a crystal, ceramic resonator, or any suitable external clock source (XTAL1 = Input, XTAL2 = Output). The crystal must be AT cut, 1 MHz to 8 MHz maximum, with a series resistance (RS) less than or equal to 100 . The on-chip oscillator can be driven with a suitable external clock source. The crystal must be connected across XTAL1 and XTAL2 using the recommended capacitors from each pin to ground. The typical capacitor value is 10 pF for 8 MHz. Also check with the crystal supplier for the optimum capacitance.
XTAL1 C1
XTAL1
XTAL1
XTAL2 C2
XTAL2
XTAL2
Crystal C1, C2 = 10 pF * f = 8 MHz
External Clock
Ceramic Resonator f = 8 MHz
*Note: preliminary value.
Figure 28.Oscillator Configuration Maxim's IR MCU supports crystal, resonator, and oscillator. Most resonators have a frequency tolerance of less than 0.5%, which is enough for remote control application. Resonator has a very fast startup time, which is around few hundred microseconds. Most crystals have a frequency tolerance of less than 50 ppm (0.005%). However, crystal needs longer startup time than the resonator. The large loading capacitance slows down the oscillation startup time. Maxim(R) suggests not to use more than 10 pF loading capacitor for the crystal. If the stray capacitance of the PCB or the crystal is high, the loading capacitance C1 and C2 must be reduced further to ensure stable oscillation before the TPOR (Power-On Reset time is typically 5-6 ms, see Table 20 on page 85). For Stop Mode Recovery operation, bit 5 of SMR register allows you to select the Stop Mode Recovery delay, which is the TPOR. If Stop Mode Recovery delay is not selected, the MCU executes instruction immediately after it wakes up from the
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STOP mode. If resonator or crystal is used as a clock source then Stop Mode Recovery delay has to be selected (bit 5 of SMR = 1). For resonator and crystal oscillator, the oscillation ground must go directly to the ground pin of the microcontroller. The oscillation ground must use the shortest distance from the microcontroller ground pin and it must be isolated from other connections.
Power Management
Power-On Reset A timer circuit clocked by a dedicated on-board RC-oscillator is used for the Power-on reset timer function. The POR time allows VDD and the oscillator circuit to stabilize before instruction execution begins. The POR timer circuit is a one-shot timer triggered by one of three conditions:
* * *
Power Fail to Power OK status, including Waking up from VBO Standby Stop Mode Recovery (if D5 of SMR = 1) WDT Timeout
The POR timer is 2.5 ms minimum. Bit 5 of the Stop Mode Register determines whether the POR timer is bypassed after Stop Mode Recovery (typical for external clock). HALT Mode This instruction turns OFF the internal CPU clock, but not the XTAL oscillation. The counter/timers and external interrupts IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, and IRQ5 remain active. The devices are recovered by interrupts, either externally or internally generated. An interrupt request must be executed (enabled) to exit HALT mode. After the interrupt service routine, the program continues from the instruction after HALT mode. STOP Mode This instruction turns OFF the internal clock and external crystal oscillation, reducing the standby current to 10 A or less. STOP mode is terminated only by a reset, such as WDT timeout, POR, SMR or external reset. This condition causes the processor to restart the application program at address 000CH. To enter STOP (or HALT) mode, first flush the instruction pipeline to avoid suspending execution in mid-instruction. Execute a NOP (Opcode = FFH) immediately before the appropriate sleep instruction, as follows:
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FF 6F
NOP STOP
; clear the pipeline ; enter STOP mode
or
FF 7F NOP HALT ; clear the pipeline ; enter HALT Mode
Port Configuration
Port Configuration Register The Port Configuration (PCON) register (see Figure 29) configures the comparator output on Port 3. It is located in the expanded register 2 at Bank F, location 00. PCON(FH)00h
D7 D6 D5 D4 D3 D2 D1 D0
Comparator Output Port 3 0 P34, P37 Standard Output* 1 P34, P37 Comparator Output Port 1 0: Open-Drain 1: Push-Pull* Port 0 0: Open-Drain 1: Push-Pull* Reserved (Must be 1)
*Default setting after reset.
Figure 29. Port Configuration Register (PCON) (Write Only) Comparator Output Port 3 (D0) Bit 0 controls the comparator used in Port 3. A 1 in this location brings the comparator outputs to P34 and P37, and a 0 releases the Port to its standard I/O configuration. Port 1 Output Mode (D1)
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Bit 1 controls the output mode of port 1. A 1 in this location sets the output to push-pull, and a 0 sets the output to open-drain. Port 0 Output Mode (D2) Bit 2 controls the output mode of port 0. A 1 in this location sets the output to push-pull, and a 0 sets the output to open-drain.
Stop Mode Recovery
Stop Mode Recovery Register This register selects the clock divide value and determines the mode of Stop Mode Recovery (see Figure 30). All bits are write only except bit 7, which is read only. Bit 7 is a Flag bit that is hardware set on the condition of Stop recovery and reset by a power-on cycle. Bit 6 controls whether a low level or a high level at the XOR-gate input (see Figure 32 on page 54) is required from the recovery source. Bit 5 controls the reset delay after recovery. Bits D2, D3, and D4 of the SMR register specify the source of the Stop Mode Recovery signal. Bits D0 determines if SCLK/TCLK are divided by 16 or not. The SMR is located in Bank F of the Expanded Register Group at address 0BH. SMR(0F)0Bh
D7 D6 D5 D4 D3 D2 D1 D0 SCLK/TCLK Divide-by-16 0 OFF * * 1 ON Reserved (Must be 0)
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Stop Mode Recovery Source 000 POR Only * 001 Reserved 010 P31 011 P32 100 P33 101 P27 110 P2 NOR 0-3 111 P2 NOR 0-7 Stop Delay 0 OFF 1 ON * * * * Stop Recovery Level * * * 0 Low * 1 High Stop Flag 0 POR * 1 Stop Recovery * *
*Default setting after reset. * *Default setting after reset and Stop Mode Recovery. * * *At the XOR gate input. * * * *Default setting after reset. Recommended to be set to 1 if using a crystal or resonator clock source.
Figure 30. Stop Mode Recovery Register SCLK/TCLK Divide-by-16 Select (D0) D0 of the SMR controls a divide-by-16 prescaler of SCLK/TCLK (see Figure 31). This control selectively reduces device power consumption during normal processor execution (SCLK control) and/or HALT mode (where TCLK sources interrupt logic). After Stop Mode Recovery, this bit is set to a 0.
OSC
2
16
SMR, D0
SCLK TCLK
Figure 31.SCLK Circuit
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Stop Mode Recovery Source (D2, D3, and D4) These three bits of the SMR specify the wake-up source of the Stop recovery (see Figure 32 and Table 14). Stop Mode Recovery Register 2--SMR2(F)0Dh Table 13 lists and briefly describes the fields for this register. Table 13. SMR2(F)0Dh:Stop Mode Recovery Register 2*
Field Reserved Recovery Level Reserved Source Bit Position 7-------6-------5-------432-W W Value 0 0 1 0 000 001 010 011 100 101 110 111 00

Description Reserved (Must be 0) Low High Reserved (Must be 0) A. POR Only B. NAND of P23-P20 C. NAND of P27-P20 D. NOR of P33-P31 E. NAND of P33-P31 F. NOR of P33-P31, P00, P07 G. NAND of P33-P31, P00, P07 H. NAND of P33-P31, P22-P20 Reserved (Must be 0)
Reserved
------10
*Port pins configured as outputs are ignored as an SMR source. Indicates the value upon Power-On Reset.
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SMR D4 D3 D2 0 00 VCC SMR D4 D3 D2 0 10 P31 P23 SMR D4 D3 D2 0 11 P32 P27 SMR D4 D3 D2 1 00 P33 P20 VCC
SMR2 D4 D3 D2 0 00 SMR2 D4 D3 D2 0 01
P20
SMR2 D4 D3 D2 0 10
P31 P32 P33
SMR2 D4 D3 D2 0 11
SMR D4 D3 D2 1 01 P27 SMR D4 D3 D2 110
P31 P32 P33 P31 P32 P33 P00 P31 P32 P33 P00 P31 P32 P33 P20 P21
SMR2 D4 D3 D2 1 00
P20 P23 P20 P27
SMR2 D4 D3 D2 1 01
SMR D4 D3 D2 1 11
SMR2 D4 D3 D2 110
SMR D6
SMR2 D4 D3 D2 1 11
To RESET and WDT Circuitry (Active Low)
SMR2 D6
Figure 32. Stop Mode Recovery Source
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Table 14. Stop Mode Recovery Source
SMR:432 D4 0 0 0 0 1 1 1 1 D3 0 0 1 1 0 0 1 1 D2 0 1 0 1 0 1 0 1 Operation Description of Action POR and/or external reset recovery Reserved P31 transition P32 transition P33 transition P27 transition Logical NOR of P20 through P23 Logical NOR of P20 through P27
Note:
Any Port 2 bit defined as an output drives the corresponding input to the default state. This condition allows the remaining inputs to control the AND/OR function. See SMR2 register on page 56 for other recover sources. Stop Mode Recovery Delay Select (D5) This bit, if low, disables the TPOR delay after Stop Mode Recovery. The default configuration of this bit is 1. If the `fast' wake up is selected, the Stop Mode Recovery source must be kept active for at least 10 TpC.
Note:
This bit must be set to 1 if using a crystal or resonator clock source. The TPOR delay allows the clock source to stabilize before executing instructions. Stop Mode Recovery Edge Select (D6) A 1 in this bit position indicates that a High level on any one of the recovery sources wakes the Crimzon ZLR32300 from STOP mode. A 0 indicates Low level recovery. The default is 0 on POR. Cold or Warm Start (D7) This bit is read only. It is set to 1 when the device is recovered from STOP mode. The bit is set to 0 when the device reset is other than Stop Mode Recovery.
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Stop Mode Recovery Register 2 (SMR2) This register determines the mode of Stop Mode Recovery for SMR2 (see
Figure 33).
SMR2(0F)Dh
D7 D6 D5 D4 D3 D2 D1 D0
Reserved (Must be 0) Reserved (Must be 0) Stop Mode Recovery Source 2 000 POR Only * 001 NAND P20, P21, P22, P23 010 NAND P20, P21, P22, P23, P24, P25, P26, P27 011 NOR P31, P32, P33 100 NAND P31, P32, P33 101 NOR P31, P32, P33, P00, P07 110 NAND P31, P32, P33, P00, P07 111 NAND P31, P32, P33, P20, P21, P22 Reserved (Must be 0) Recovery Level * * 0 Low * 1 High Reserved (Must be 0)
Note: If used in conjunction with SMR, either of the two specified events causes a Stop Mode Recovery.
*Default setting after reset. **At the XOR gate input.
Figure 33. Stop Mode Recovery Register 2 ((0F)DH:D2-D4, D6 Write Only) If SMR2 is used in conjunction with SMR, either of the specified events causes a Stop Mode Recovery. Note: Port pins configured as outputs are ignored as an SMR or SMR2 recovery source. For example, if the NAND or P23-P20 is selected as the recovery source and P20 is configured as an
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output, the remaining SMR pins (P23-P21) form the NAND equation.
Watchdog Timer Mode
Watchdog Timer Mode Register (WDTMR) The Watchdog Timer is a retriggerable one-shot timer that resets the Z8 if it reaches its terminal count. The WDT must initially be enabled by executing the WDT instruction. On subsequent executions of the WDT instruction, the WDT is refreshed. The WDT circuit is driven by an on-board RC-oscillator. The WDT instruction affects the Zero (Z), Sign (S), and Overflow (V) Flags. The POR clock source the internal RC-oscillator. Bits 0 and 1 of the WDT register control a tap circuit that determines the minimum timeout period. Bit 2 determines whether the WDT is active during HALT, and Bit 3 determines WDT activity during Stop. Bits 4 through 7 are reserved (see Figure 34). This register is accessible only during the first 60 processor cycles (120 XTAL clocks) from the execution of the first instruction after Power-on reset, Watchdog Reset, or a Stop Mode Recovery (see Figure 33 on page 56). After this point, the register cannot be modified by any means (intentional or otherwise). The WDTMR cannot be read. The register is located in Bank F of the Expanded Register Group at address location 0Fh. It is organized as displayed in Figure 34. WDTMR(0F)0Fh
D7 D6 D5 D4 D3 D2 D1 D0
WDT TAP INT RC OSC 00 10 ms min. 01* 20 ms min. 10 40 ms min. 11 160 ms min. WDT During HALT 0 OFF 1 ON * WDT During Stop 0 OFF 1 ON * Reserved (Must be 0)
*Default setting after reset.
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Figure 34. Watchdog Timer Mode Register (Write Only)
WDT Time Select (D0, D1) This bit selects the WDT time period. It is configured as indicated in Table 15. Table 15. Watchdog Timer Time Select
D1 0 0 1 1 D0 0 1 0 1 Timeout of Internal RC-Oscillator 10 ms min. 20 ms min. 40 ms min. 160 ms min.
WDTMR During Halt (D2) This bit determines whether or not the WDT is active during HALT mode. A 1 indicates active during HALT. The default is 1. See Figure 35.
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5 Clock Filter
*CLR2 CLK
18 Clock RESET RESET Generator Internal RESET Active High WDT TAP SELECT
XTAL
Internal RC Oscillator. Low Operating Voltage Det. POR 10 ms 20 ms 40 ms 160 CLK WDT/POR Counter Chain *CLR1
VDD VBO WDT From Stop Mode Recovery Source Stop Delay Select (SMR)
+ -
VDD 12-ns Glitch Filter
* CLR1 and CLR2 enable the WDT/POR and 18 Clock Reset timers respectively upon a Low-to-High input translation.
Figure 35. Resets and WDT WDTMR During STOP (D3) This bit determines whether or not the WDT is active during STOP mode. A 1 indicates active during Stop. The default is 1. ROM Selectable Options There are seven ROM Selectable Options to choose from based on ROM code requirements. These are listed in Table 16.
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Table 16. ROM Selectable Options
Port 00-03 Pull-Ups Port 04-07 Pull-Ups Port 10-13 Pull-Ups Port 14-17 Pull-Ups Port 20-27 Pull-Ups Port 3 Pull-Ups ON/OFF ON/OFF ON/OFF ON/OFF ON/OFF ON/OFF
Watchdog Timer at Power-On Reset ON/OFF
Voltage Brownout/Standby An on-chip Voltage Comparator checks that the VDD is at the required level for correct operation of the device. Reset is globally driven when VDD falls below VBO. A small drop in VDD causes the XTAL1 and XTAL2 circuitry to stop the crystal or resonator clock. If the VDD is allowed to stay above VRAM, the RAM content is preserved. When the power level is returned to above VBO, the device performs a POR and functions normally.
Low-Voltage Detection
Low-Voltage Detection Register--LVD(D)0CH Note:
Field LVD
Voltage detection does not work at STOP mode.
Bit Position 76543-------2-------1-------0
*Default after POR.
Description Reserved No Effect R R R/W 1 0* 1 0* 1 0* HVD Flag set HVD Flag reset LVD Flag set LVD Flag reset Enable VD Disable VD
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Note:
Do not modify register P01M while checking a low-voltage condition. Switching noise of both ports 0 and 1 together might trigger the LVD Flag. Voltage Detection and Flags The Voltage Detection register (LVD, register 0Ch at the expanded register bank 0Dh) offers an option of monitoring the VCC voltage. The voltage detection is enabled when bit 0 of LVD register is set. Once voltage detection is enabled, the VCC level is monitored in real time. The Flags in the LVD register valid 20 s after voltage detection is enabled. The HVD Flag (bit 2 of the LVD register) is set only if VCC is higher than VHVD. The LVD Flag (bit 1 of the LVD register) is set only if VCC is lower than the VLVD. When voltage detection is enabled, the LVD Flag also triggers IRQ5. The IRQ bit 5 latches the low voltage condition until it is cleared by instructions or reset. The IRQ5 interrupt is served if it is enabled in the IMR register. Otherwise, bit 5 of IRQ register is latched as a Flag only.
Note:
If it is necessary to receive an LVD interrupt upon power-up at an operating voltage lower than the low-battery detect threshold, enable interrupts using the Enable Interrupt (EI) instruction prior to enabling the voltage detection.
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Expanded Register File Control Registers (0D)
The expanded register file control registers (0D) are displayed in Figure 36 on page 63 through Figure 40 on page 68.
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CTR0(0D)00h
D7 D6 D5 D4 D3 D2 D1 D0
0 P34 as Port Output * 1 Timer8 Output
0 Disable T8 Timeout Interrupt** 1 Enable T8 Timeout Interrupt 0 Disable T8 Data Capture Interrupt** 1 Enable T8 Data Capture Interrupt
00 01 10 11 R R W W
SCLK on T8** SCLK/2 on T8 SCLK/4 on T8 SCLK/8 on T8 0 No T8 Counter Timeout** 1 T8 Counter Timeout Occurred 0 No Effect 1 Reset Flag to 0
0 Modulo-N* 1 Single Pass R R W W 0 T8 Disabled * 1 T8 Enabled 0 Stop T8 1 Enable T8
*Default setting after reset. **Default setting after reset. Not reset with a Stop Mode Recovery.
Figure 36.TC8 Control Register ((0D)O0H: Read/Write Except Where Noted)
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CTR1(0D)01h
D7 D6 D5 D4 D3 D2 D1 D0 TRANSMIT Mode* R/W 0 T16_OUT is 0 initially* 1 T16_OUT is 1 initially DEMODULATION Mode R 0 No Falling Edge Detection R 1 Falling Edge Detection W 0 No Effect W 1 Reset Flag to 0 TRANSMIT Mode* R/W 0 T8_OUT is 0 initially* 1 T8_OUT is 1 initially DEMODULATION Mode R 0 No Rising Edge Detection
R 1 Rising Edge Detection
W 0 No Effect W 1 Reset Flag to 0 TRANSMIT Mode* 0 0 Normal Operation* 0 1 PING-PONG Mode 1 0 T16_OUT = 0 1 1 T16_OUT = 1 DEMODULATION Mode 0 0 No Filter 0 1 4 SCLK Cycle Filter 1 0 8 SCLK Cycle Filter 1 1 Reserved TRANSMIT Mode/T8/T16 Logic 0 0 AND** 0 1 OR 1 0 NOR 1 1 NAND DEMODULATION Mode 0 0 Falling Edge Detection 0 1 Rising Edge Detection 1 0 Both Edge Detection 1 1 Reserved TRANSMIT Mode 0 P36 as Port Output * 1 P36 as T8/T16_OUT
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CTR1(0D)01h
DEMODULATION Mode 0 P31 as Demodulator Input 1 P20 as Demodulator Input TRANSMIT/DEMODULATION Mode 0 TRANSMIT Mode * *Default setting after reset. 1 DEMODULATION Mode **Default setting after reset. Not reset with a Stop Mode
Recovery.
Figure 37.T8 and T16 Common Control Functions ((0D)01H: Read/Write)
Note:
Ensure differentiating the TRANSMIT mode from DEMODULATION mode. Depending on which of these two modes is operating, the CTR1 bit has different functions. Changing from one mode to another cannot be performed
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without disabling the counter/timers. CTR2(0D)02h
D7 D6 D5 D4 D3 D2 D1 D0
0 P35 is Port Output * 1 P35 is TC16 Output 0 Disable T16 Timeout Interrupt* 1 Enable T16 Timeout Interrupt 0 Disable T16 Data Capture Interrupt** 1 Enable T16 Data Capture Interrupt 0 0 1 1 R R W W 0 1 0 1 0 1 0 1 SCLK on T16** SCLK/2 on T16 SCLK/4 on T16 SCLK/8 on T16 No T16 Timeout** T16 Timeout Occurs No Effect Reset Flag to 0
TRANSMIT Mode 0 Modulo-N for T16* 0 Single Pass for T16 Demodulator Mode 0 T16 Recognizes Edge 1 T16 Does Not Recognize Edge R R W *Default setting after reset. **Default setting after reset. Not reset with a Stop Mode W
Recovery.
0 1 0 1
T16 Disabled * T16 Enabled Stop T16 Enable T16
Figure 38. T16 Control Register ((0D) 2H: Read/Write Except Where Noted)
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CTR3(0D)03h
D7 D6 D5 D4 D3 D2 D1 D0 Reserved 0 No Effect 1 Always reads 11111 Sync Mode 0** Disable Sync Mode 1 Enable Sync Mode T8 Enable 0* Counter Disabled 1 Counter Enabled 0 Stop Counter 1 Enable Counter T16 Enable 0* Counter Disabled 1 Counter Enabled 0 Stop Counter 1 Enable Counter
*Default setting after reset. **Default setting after reset. Not reset with a Stop Mode Recovery.
Figure 39. T8/T16 Control Register (0D)03H: Read/Write (Except Where Noted) Note: If Sync Mode is enabled, the first pulse of T8 (carrier) is always synchronized with T16 (demodulated signal). It can always provide a full carrier pulse.
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LVD(0D)0Ch
D7 D6 D5 D4 D3 D2 D1 D0
Voltage Detection 0: Disable * 1: Enable LVD Flag (Read only) 0: LVD Flag reset * 1: LVD Flag set HVD Flag (Read only) 0: HVD Flag reset * 1: HVD Flag set Reserved (Must be 0)
*Default setting after reset.
Figure 40. Voltage Detection Register Note: Do not modify register P01M while checking a low-voltage condition. Switching noise of both ports 0 and 1 together might trigger the LVD Flag.
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Expanded Register File Control Registers (0F)
The expanded register file control registers (0F) are displayed in Figure 41 on page 69 through Figure 54 on page 79. PCON(0F)00h
D7 D6 D5 D4 D3 D2 D1 D0
Comparator Output Port 3 0 P34, P37 Standard Output * 1 P34, P37 Comparator Output Port 1 0: Open-Drain 1: Push-Pull* Port 0 0: Open-Drain 1: Push-Pull * Reserved (Must be 1)
*Default setting after reset.
Figure 41. Port Configuration Register (PCON)(0F)00H: Write Only)
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SMR(0F)0Bh
D7 D6 D5 D4 D3 D2 D1 D0
SCLK/TCLK Divide-by-16 0 OFF * 1 ON Reserved (Must be 0) Stop Mode Recovery Source 000 POR Only * * 001 Reserved 010 P31 011 P32 100 P33 101 P27 110 P2 NOR 0-3 111 P2 NOR 0-7 Stop Delay 0 OFF 1 ON * * * * Stop Recovery Level * * * 0 Low ** 1 High Stop Flag 0 POR * * * * * 1 Stop Recovery * *
*Default setting after reset. * *Default setting after reset and Stop Mode Recovery. * * *At the XOR gate input. * * * *Default setting after reset. Recommended to be set to 1 if using a crystal or resonator clock source.Not reset with Stop Mode Recovery. * * * * *Default setting after Power-On Reset.
Figure 42. Stop Mode Recovery Register ((0F)0BH: D6-D0=Write Only, D7=Read Only)
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SMR2(0F)0Dh
D7 D6 D5 D4 D3 D2 D1 D0
Reserved (Must be 0)
Reserved (Must be 0)
Stop Mode Recovery Source 2 000 POR Only * 001 NAND P20, P21, P22, P23 010 NAND P20, P21, P22, P23, P24, P25, P26, P27 011 NOR P31, P32, P33 100 NAND P31, P32, P33 101 NOR P31, P32, P33, P00, P07 110 NAND P31, P32, P33, P00, P07 111 NAND P31, P32, P33, P20, P21, P22 Reserved (Must be 0)
Recovery Level * * 0 Low 1 High Reserved (Must be 0)
Note: If used in conjunction with SMR, either of the two specified events causes a Stop Mode Recovery.
*Default setting after reset. Not reset with a Stop Mode Recovery. * *At the XOR gate input.
Figure 43. Stop Mode Recovery Register 2 ((0F)0DH:D2-D4, D6 Write Only)
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WDTMR(0F)0Fh
D7 D6 D5 D4 D3 D2 D1 D0
WDT TAP INT RC OSC 00 10 ms min. 01* 20 ms min. 10 40 ms min. 11 160 ms min. WDT During HALT 0 OFF 1 ON * WDT During Stop 0 OFF 1 ON * Reserved (Must be 0)
*Default setting after reset. Not reset wit a Stop Mode Recovery.
Figure 44. Watchdog Timer Register ((0F) 0FH: Write Only)
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Functional Description
Crimzon(R) ZLR32300 Product Specification
73
Standard Control Registers
The standard control registers are displayed in Figure 45 through Figure 54 on page 79. R246P2M(F6H)
D7 D6 D5 D4 D3 D2 D1 D0
P27-P20 I/O Definition 0 Defines bit as OUTPUT 1 Defines bit as INPUT *
*Default setting after reset. Not reset wit a Stop Mode Recovery.
Figure 45. Port 2 Mode Register (F6H: Write Only)
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Functional Description
Crimzon(R) ZLR32300 Product Specification
74
R247P3M(F7H)
D7 D6 D5 D4 D3 D2 D1 D0
0: Port 2 Open Drain * 1: Port 2 Push-Pull 0= P31, P32 DIGITAL Mode* 1= P31, P32 ANALOG Mode
Reserved (Must be 0)
*Default setting after reset. Not reset wit a Stop Mode recovery.
Figure 46. Port 3 Mode Register (F7H: Write Only)
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Functional Description
Crimzon(R) ZLR32300 Product Specification
75
R248 P01M(F8H)
D7 D6 D5 D4 D3 D2 D1 D0
P00-P03 Mode 0: Output 1: Input * Reserved (Must be 0) Reserved (Must be 1)
P17-P10 Mode 0: Byte Output 1: Byte Input* Reserved (Must be 0) P07-P04 Mode 0: Output 1: Input * Reserved (Must be 0)
*Default setting after reset; only P00, P01, and P07 are available on Crimzon ZLR32300 20-pin configurations.
Figure 47.Port 0 and 1 Mode Register (F8H: Write Only)
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Functional Description
Crimzon(R) ZLR32300 Product Specification
76
R249 IPR(F9H)
D7 D6 D5 D4 D3 D2 D1 D0
Interrupt Group Priority 000 Reserved 001 C > A > B 010 A > B >C 011 A > C > B 100 B > C > A 101 C > B > A 110 B > A > C 111 Reserved IRQ1, IRQ4, Priority (Group C) 0: IRQ1 > IRQ4 1: IRQ4 > IRQ1 IRQ0, IRQ2, Priority (Group B) 0: IRQ2 > IRQ0 1: IRQ0 > IRQ2 IRQ3, IRQ5, Priority (Group A) 0: IRQ5 > IRQ3 1: IRQ3 > IRQ5 Reserved; must be 0
Figure 48.Interrupt Priority Register (F9H: Write Only)
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Functional Description
Crimzon(R) ZLR32300 Product Specification
77
R250 IRQ(FAH)
D7 D6 D5 D4 D3 D2 D1 D0
IRQ0 = P32 Input IRQ1 = P33 Input IRQ2 = P31 Input IRQ3 = T16 IRQ4 = T8 IRQ5 = LVD Inter Edge P31 P32 = 00 P31 P32 = 01 P31 P32 = 10 P31 P32 = 11
Figure 49.Interrupt Request Register (FAH: Read/Write) R251 IMR(FBH)
D7 D6 D5 D4 D3 D2 D1 D0
1 Enables IRQ5-IRQ0 (D0 = IRQ0)
Reserved (Must be 0) 0 Master Interrupt Disable * 1 Master Interrupt Enable * *
*Default setting after reset. * *Only by using EI, DI instruction; DI is required before changing the IMR register.
Figure 50.Interrupt Mask Register (FBH: Read/Write)
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Functional Description
Crimzon(R) ZLR32300 Product Specification
78
R252 Flags(FCH)
D7 D6 D5 D4 D3 D2 D1 D0 User Flag F1 User Flag F2 Half Carry Flag Decimal Adjust Flag Overflow Flag Sign Flag Zero Flag Carry Flag
Figure 51.Flag Register (FCH: Read/Write) R253 RP(FDH)
D7 D6 D5 D4 D3 D2 D1 D0
Expanded Register Bank Pointer
Working Register Pointer Default setting after reset = 0000 0000
Figure 52.Register Pointer (FDH: Read/Write)
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Functional Description
Crimzon(R) ZLR32300 Product Specification
79
R254 SPH(FEH)
D7 D6 D5 D4 D3 D2 D1 D0
General-Purpose Register
Figure 53.Stack Pointer High (FEH: Read/Write) R255 SPL(FFH)
D7 D6 D5 D4 D3 D2 D1 D0
Stack Pointer Low Byte (SP7-SP0)
Figure 54.Stack Pointer Low (FFH: Read/Write)
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Functional Description
Crimzon(R) ZLR32300 Product Specification
80
Electrical Characteristics
Absolute Maximum Ratings
Stresses greater than those listed in Table 17 might cause permanent damage to the device. This rating is a stress rating only. Functional operation of the device at any condition above those indicated in the operational sections of these specifications is not implied. Exposure to absolute maximum rating conditions for an extended period might affect device reliability. Table 17.Absolute Maximum Ratings
Parameter Ambient temperature under bias Storage temperature Voltage on any pin with respect to VSS Voltage on VDD pin with respect to VSS Maximum current on input and/or inactive output pin Maximum output current from active output pin Maximum current into VDD or out of VSS
1This voltage applies to all pins except the following: V and RESET. DD
Minimum Maximum 0 -65 -0.3 -0.3 -5 -25 +70 +150 +4.0 +3.6 +5 +25 75
Units C C V V A mA mA
Notes
1
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Electrical Characteristics
Crimzon(R) ZLR32300 Product Specification
81
Standard Test Conditions
The characteristics listed in this product specification apply for standard test conditions as noted. All voltages are referenced to GND. Positive current flows into the referenced pin (see Figure 55 on page 81).
From Output Under Test
150 pF
Figure 55.Test Load Diagram
Capacitance
Table 18 lists the capacitances. Table 18.Capacitance
Parameter Input capacitance Output capacitance I/O capacitance Maximum 12 pF 12 pF 12 pF
Note: TA = 25 C, VCC = GND = 0 V, f = 1.0 MHz, unmeasured pins returned to GND
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Electrical Characteristics
Crimzon(R) ZLR32300 Product Specification
82
DC Characteristics
Table 19.DC Characteristics
TA= 0 C to +70 C Symbol Parameter VCC Supply Voltage VCH Clock Input High Voltage VCL Clock Input Low Voltage VIH Input High Voltage VIL Input Low Voltage VOH1 Output High Voltage VOH2 Output High Voltage (P36, P37, P00, P01) Output Low Voltage VOL1 VOL2 Output Low Voltage (P00, P01, P36, P37) VOFFSET Comparator Input Offset Voltage VREF Comparator Reference Voltage Input Leakage IIL RPU Pull-Up Resistance Minimum Typ(7) Maximum Units Conditions Notes 2.0 3.6 V See notes 5 5 2.0-3.6 0.8VCC VCC+0.3 V Driven by External Clock Generator 2.0-3.6 VSS-0.3 0.5 V Driven by External Clock Generator 2.0-3.6 0.7VCC VCC+0.3 V 2.0-3.6 VSS-0.3 0.2 VCC V 2.0-3.6 VCC-0.4 V IOH = -0.5 mA 2.0-3.6 VCC-0.8 V IOH = -7 mA VCC
2.0-3.6 2.0-3.6
0.4 0.8
V V
IOL = 4.0 mA IOL = 10 mA
2.0-3.6 2.0-3.6 0
25 VDD -1.75 1 675 275 1 3 5 1.6 2.0
mV V
2.0-3.6
-1 225 75
A K K A mA mA mA mA
IOL ICC ICC1
Output Leakage Supply Current Standby Current (HALT mode)
2.0-3.6 2.0 3.6 2.0 3.6
-1 1.2 2.2 0.5 0.8
VIN = 0 V, VCC Pull-ups disabled VIN = 0 V; Pullups selected by mask option VIN = 0 V, VCC at 8.0 MHz 1, 2 at 8.0 MHz 1, 2 VIN = 0 V, VCC at 1, 2, 6 8.0 MHz 1, 2, 6 Same as above
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Electrical Characteristics
Crimzon(R) ZLR32300 Product Specification
83
Table 19.DC Characteristics (Continued)
TA= 0 C to +70 C Symbol Parameter ICC2 Standby Current (STOP mode) VCC 2.0 3.6 2.0 3.6 Minimum Typ(7) Maximum Units A 8 1.5 A 10 2.1 A 20 4.7 A 30 7.4 Conditions Notes VIN = 0 V, VCC 3 3 WDT is not 3 Running 3 Same as above VIN = 0 V, VCC WDT is Running Same as above Measured at 1.3 V 4 8 MHz maximum Ext. CLK Freq.
ILV VBO VLVD VHVD
Standby Current (Low Voltage) VCC Low Voltage Protection Vcc Low Voltage Detection Vcc High Voltage Detection
1.0 1.8 2.4 2.7
6 2.0
A V V V
Notes: 1. All outputs unloaded, inputs at rail. 2. CL1 = CL2 = 100 pF. 3. Oscillator stopped. 4. Oscillator stops when VCC falls below VBO limit. 5. It is strongly recommended to add a filter capacitor (minimum 0.1 F), physically close to VDD and GND if operating voltage fluctuations are anticipated, such as those resulting from driving an Infrared LED. 6. Comparator and Timers are on. Interrupt disabled. 7. Typical values shown are at 25 C.
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Electrical Characteristics
Crimzon(R) ZLR32300 Product Specification
84
AC Characteristics
Figure 56 on page 84 and Table 20 on page 85 describe the AC characteristics. 1 Clock 2 7 2 3
3
7 TIN
4 6
5
IRQN 8 9
Clock Setup 11
Stop Mode Recovery Source
10
Figure 56. AC Timing Diagram
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Electrical Characteristics
Crimzon(R) ZLR32300 Product Specification
85
Table 20.AC Characteristics
TA=0 C to +70 C 8.0 MHz Watchdog Timer Mode Register Minimum Maximum Units Notes (D1, D0) 121 DC 25 37 100 70 3TpC 8TpC 100 100 70 10TpC 12 10TpC 11 Tost 12 Twdt Oscillator Start-Up Time Watchdog Timer Delay Time 2.0-3.6 2.0-3.6 2.0-3.6 2.0-3.6 2.0-3.6 2.0-3.6 10 20 40 160 2.5 10 5TpC ms ms ms ms ms ns ns ns ns ns ns ns 1 1 1 1 1 1 1 1, 2 1, 2 3 4 4 0, 0 0, 1 1, 0 1, 1
No Symbol 1 TpC 2 TrC,TfC 3 TwC 4 TwTinL 5 TwTinH 6 TpTin
Parameter Input Clock Period Clock Input Rise and Fall Times Input Clock Width Timer Input Low Width Timer Input High Width Timer Input Period
VCC 2.0-3.6 2.0-3.6 2.0-3.6 2.0 3.6 2.0-3.6 2.0-3.6 2.0-3.6 2.0 3.6 2.0-3.6 2.0-3.6
7 TrTin,TfTin Timer Input Rise and Fall Timers 8 TwIL 9 TwIH 10 Twsm Interrupt Request Low Time Interrupt Request Input High Time Stop Mode Recovery Width Spec
13 TPOR
Power-On Reset
Notes: 1.Timing Reference uses 0.9 VCC for a logic 1 and 0.1 VCC for a logic 0. 2.Interrupt request through Port 3 (P33-P31). 3.SMR - D5 = 1. 4.SMR - D5 = 0.
19-4623; Rev 0; 5/09
Electrical Characteristics
Crimzon(R) ZLR32300 Product Specification
86
Packaging
Package information for all versions of Crimzon ZLR32300 is displayed in Figure 57 through Figure 63 on page 91.
Figure 57.20-Pin PDIP Package Diagram
Figure 58.20-Pin SOIC Package Diagram
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Packaging
Crimzon(R) ZLR32300 Product Specification
87
Figure 59. 20-Pin SSOP Package Diagram
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Packaging
Crimzon(R) ZLR32300 Product Specification
88
Figure 60. 28-Pin SOIC Package Diagram
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Packaging
Crimzon(R) ZLR32300 Product Specification
89
Figure 61. 28-Pin PDIP Package Diagram
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Packaging
Crimzon(R) ZLR32300 Product Specification
90
D 28 15 C SYMBOL A E H A1 A2 B C 1 14 DETAIL A D E e MIN 1.73 0.05 1.68 0.25 0.09 10.07 5.20 10.20 5.30 0.65 TYP 7.65 0.63 7.80 0.75 7.90 0.95 0.301 0.025 MILLIMETER NOM 1.86 0.13 1.73 MAX 1.99 0.21 1.78 0.38 0.20 10.33 5.38 MIN 0.068 0.002 0.066 0.010 0.004 0.397 0.205 0.006 0.402 0.209 0.0256 TYP 0.307 0.030 0.311 0.037 INCH NOM 0.073 0.005 0.068 MAX 0.078 0.008 0.070 0.015 0.008 0.407 0.212
Q1
H L A2
A1
A
e
B SEATING PLANE CONTROLLING DIMENSIONS: MM LEADS ARE COPLANAR WITHIN .004 INCHES. L
0-8
DETAIL 'A'
Figure 62. 28-Pin SSOP Package Diagram
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Packaging
Crimzon(R) ZLR32300 Product Specification
91
D
48 25
c
E
H
1
24 Detail A
A2 1
A
CONTROLLING DIMENSIONS : MM LEADS ARE COPLANAR WITHIN .004 INCH
SEATING PLANE e b
L 0-8
Detail A
Figure 63. 48-Pin SSOP Package Design Note: Contact Maxim(R) on the actual bonding diagram and coordinate for chip-on-board assembly.
19-4623; Rev 0; 5/09
Packaging
Crimzon(R) ZLR32300 Product Specification
92
Ordering Information
The following table provides part number, description, and memory size of Crimzon ZLR32300.
Memory Size 32 K Part Number ZLR32300H4832G ZLR32300H2832G ZLR32300P2832G ZLR32300S2832G ZLR32300H2032G ZLR32300P2032G ZLR32300S2032G 24 K ZLR32300H4824G ZLR32300H2824G ZLR32300P2824G ZLR32300S2824G ZLR32300H2024G ZLR32300P2024G ZLR32300S2024G 16 K 8K 4K ZLR32300H4816G ZLR32300H4808G ZLR32300H4804G Development Tools ZLP128ICE01ZEMG* In-Circuit Emulator Description 48-pin SSOP 32 K ROM 28-pin SSOP 32 K ROM 28-pin PDIP 32 K ROM 28-pin SOIC 32 K ROM 20-pin SSOP 32 K ROM 20-pin PDIP 32 K ROM 20-pin SOIC 32 K ROM 48-pin SSOP 24 K ROM 28-pin SSOP 24 K ROM 28-pin PDIP 24 K ROM 28-pin SOIC 24 K ROM 20-pin SSOP 24 K ROM 20-pin PDIP 24 K ROM 20-pin SOIC 24 K ROM 48-pin SSOP 16 K ROM 48-pin SSOP 8 K ROM 48-pin SSOP 4 K ROM
Note: *ZLP128ICE01ZEMG has been replaced by an improved version, ZCRMZNICE01ZEMG.
ZLP323ICE01ZACG
40-PDIP/48-SSOP Accessory Kit
ZCRMZNICE01ZEMG Crimzon In-Circuit Emulator ZCRMZN00100KITG ZCRMZNICE01ZACG ZCRMZNICE02ZACG Crimzon In-Circuit Emulator Development Kit 20-Pin Accessory Kit 40/48-Pin Accessory Kit
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Ordering Information
Crimzon(R) ZLR32300 Product Specification
93
Memory Size
Part Number
Description
Note: Contact www.maxim-ic.com for the die form. For fast results, contact your local Maxim sales office for assistance in ordering the part desired.
Part Number Description
Maxim part numbers consist of a number of components, as displayed in Figure 64. The example part number ZLR32300H2832G is a Crimzon masked ROM product in a 28-pin SSOP package, with 32 KB of ROM and built with leadfree solder.
Z LR 32300 H 28 32 G Environmental Flow G = Lead Free Memory Size 32 = 32 KB 24 = 24 KB 16 = 16 KB 8 = 8 KB 4 = 4 KB Number of Pins in Package 48 = 48 Pins 40 = 40 Pins 28 = 28 Pins 20 = 20 Pins Package Type H = SSOP P = PDIP S = SOIC Product Number 32300 Product Line Crimzon ROM Maxim Product Prefix
Figure 64. Part Number Description Example
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Ordering Information
Crimzon(R) ZLR32300 Product Specification
94
Index
Numerics
16-bit counter/timer circuits 41 20-pin DIP package diagram 86 20-pin SSOP package diagram 87 28-pin DIP package diagram 89 28-pin SOICpackage diagram 88 28-pin SSOP package diagram 90 48-pin SSOP package diagram 91 8-bit counter/timer circuits 37
A
absolute maximum ratings 80 AC characteristics 84 timing diagram 84 address spaces, basic 1 architecture 1 expanded register file 23
B
basic address spaces 1 block diagram, ZLP32300 functional 4
C
capacitance 81 characteristics AC 84 DC 82 clock 48 comparator inputs/outputs 19 configuration port 0 13 port 1 14 port 2 15 port 3 16 port 3 counter/timer 18
counter/timer 16-bit circuits 41 8-bit circuits 37 brown-out voltage/standby 60 clock 48 demodulation mode count capture flowchart 39 demodulation mode flowchart 40 EPROM selectable options 60 glitch filter circuitry 35 halt instruction 49 input circuit 35 interrupt block diagram 46 interrupt types, sources and vectors 47 oscillator configuration 48 output circuit 44 ping-pong mode 43 port configuration register 50 resets and WDT 59 SCLK circuit 52 stop instruction 49 stop mode recovery register 52 stop mode recovery register 2 56 stop mode recovery source 54 T16 demodulation mode 42 T16 transmit mode 41 T16_OUT in modulo-N mode 42 T16_OUT in single-pass mode 42 T8 demodulation mode 39 T8 transmit mode 35 T8_OUT in modulo-N mode 38 T8_OUT in single-pass mode 38 transmit mode flowchart 36 voltage detection and flags 61 watchdog timer mode register 57 watchdog timer time select 58 CTR(D)01h T8 and T16 Common Functions 30 Customer Feedback Form 98
D
DC characteristics 82 demodulation mode count capture flowchart 39 flowchart 40
19-4623; Rev 0; 5/09
Index
Crimzon(R) ZLR32300 Product Specification
95
T16 42 T8 39 description pin 6
E
EPROM selectable options 60 expanded register file 21 expanded register file architecture 23 expanded register file control registers 68 flag 78 interrupt mask register 77 interrupt priority register 76 interrupt request register 77 port 0 and 1 mode register 75 port 2 configuration register 73 port 3 mode register 74 port configuration register 73 register pointer 78 stack pointer high register 79 stack pointer low register 79 stop-mode recovery register 70 stop-mode recovery register 2 71 T16 control register 66 T8 and T16 common control functions register 65 T8/T16 control register 67 TC8 control register 62 watch-dog timer register 72
HI16(D)09h register 27 HI8(D)0Bh register 26 L08(D)0Ah register 27 L0I6(D)08h register 27 program memory map 21 RAM 20 register description 60 register file 25 register pointer 24 register pointer detail 26 SMR2(F)0D1h register 35 stack 26 TC16H(D)07h register 27 TC16L(D)06h register 27 TC8H(D)05h register 28 TC8L(D)04h register 28
G
glitch filter circuitry 35
H
halt instruction, counter/timer 49
I
input circuit 35 interrupt block diagram, counter/timer 46 interrupt types, sources and vectors 47
F
features standby modes 2 functional description counter/timer functional blocks 35 CTR(D)01h register 30 CTR0(D)00h register 28 CTR2(D)02h register 32 CTR3(D)03h register 34 expanded register file 21 expanded register file architecture 23
L
low-voltage detection register 60
M
memory, program 20 modulo-N mode T16_OUT 42 T8_OUT 38
19-4623; Rev 0; 5/09
Index
Crimzon(R) ZLR32300 Product Specification
96
O
oscillator configuration 48 output circuit, counter/timer 44
program memory 20 map 21
R P
package information 20-pin DIP package diagram 86 20-pin SSOP package diagram 87 28-pin DIP package diagram 89 28-pin SOIC package diagram 88 28-pin SSOP package diagram 90 48-pin SSOP package diagram 91 pin configuration 20-pin DIP/SOIC/SSOP 6 28-pin DIP/SOIC/SSOP 7 40- and 48-pin 8 48-pin SSOP 8 pin functions port 0 (P07 - P00) 12 port 0 (P17 - P10) 13 port 0 configuration 13 port 1 configuration 14 port 2 (P27 - P20) 14 port 2 (P37 - P30) 15 port 2 configuration 15 port 3 configuration 16 port 3 counter/timer configuration 18 reset) 19 XTAL1 (time-based input 11 XTAL2 (time-based output) 11 ping-pong mode 43 port 0 configuration 13 port 0 pin function 12 port 1 configuration 14 port 1 pin function 13 port 2 configuration 15 port 2 pin function 14 port 3 configuration 16 port 3 pin function 15 port 3counter/timer configuration 18 port configuration register 50 power connections 2 power supply 6 ratings, absolute maximum 80 register 56 CTR(D)01h 30 CTR0(D)00h 28 CTR2(D)02h 32 CTR3(D)03h 34 flag 78 HI16(D)09h 27 HI8(D)0Bh 26 interrupt priority 76 interrupt request 77 interruptmask 77 L016(D)08h 27 L08(D)0Ah 27 LVD(D)0Ch 60 pointer 78 port 0 and 1 75 port 2 configuration 73 port 3 mode 74 port configuration 50, 73 SMR2(F)0Dh 35 stack pointer high 79 stack pointer low 79 stop mode recovery 52 stop mode recovery 2 56 stop-mode recovery 70 stop-mode recovery 2 71 T16 control 66 T8 and T16 common control functions 65 T8/T16 control 67 TC16H(D)07h 27 TC16L(D)06h 27 TC8 control 62 TC8H(D)05h 28 TC8L(D)04h 28 voltage detection 68 watch-dog timer 72 register description Counter/Timer2 LS-Byte Hold 27
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Index
Crimzon(R) ZLR32300 Product Specification
97
Counter/Timer2 MS-Byte Hold 27 Counter/Timer8 Control 28 Counter/Timer8 High Hold 28 Counter/Timer8 Low Hold 28 CTR2 Counter/Timer 16 Control 32 CTR3 T8/T16 Control 34 Stop Mode Recovery2 35 T16_Capture_LO 27 T8 and T16 Common functions 30 T8_Capture_HI 26 T8_Capture_LO 27 register file 25 expanded 21 register pointer 24 detail 26 reset pin function 19 resets and WDT 59
V
VCC 6 voltage brown-out/standby 60 detection and flags 61 voltage detection register 68
W
watchdog timer mode register watchdog timer mode register 57 time select 58
X
XTAL1 6 XTAL1 pin function 11 XTAL2 6 XTAL2 pin function 11
S
SCLK circuit 52 single-pass mode T16_OUT 42 T8_OUT 38 stack 26 standard test conditions 81 standby modes 2 stop instruction, counter/timer 49 stop mode recovery 2 register 56 source 54 stop mode recovery 2 56 stop mode recovery register 52
T
T16 transmit mode 41 T16_Capture_HI 27 T8 transmit mode 35 T8_Capture_HI 26 test conditions, standard 81 test load diagram 81 timing diagram, AC 84 transmit mode flowchart 36
19-4623; Rev 0; 5/09
Index
Crimzon(R) ZLR32300 Product Specification
98
Customer Support
For any comments, detail technical questions, or reporting problems, please visit Maxim's Technical Support at https://support.maxim-ic.com/micro.
19-4623; Rev 0; 5/09
Customer Support

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